The seven levels

The course is organised by topic, because a topic is what a chapter can be about. A chapter takes one subject up the ladder, which is how chapter 3 can show the same capacitor as a role, a failure mode, a number and a layout problem in one sitting.

This page is the other axis. Each level is defined here, with a test for whether you have it and a map of every section in the course that operates there. Read the course by topic, or read one level across the whole course.

The levels are a difficulty scale, not a syllabus. Nobody climbs them uniformly. A working engineer is at EE7 on the two subsystems they own and EE3 on the rest of the board, which is the ordinary shape of the job rather than a gap in it. Their purpose is to calibrate an explanation: “explain output-output-conflict at EE4” asks for the bench symptom rather than the definition, in the same way ELI15 asks for a register.

Parts (EE1) ¶

The question you can answer: what is that component?

Ohm’s law, and what a resistor, capacitor, inductor, diode and transistor each do on their own. This is the floor the course assumes rather than teaches, and most people arriving from software already have it.

• A board is a few kinds of thing, the whole vocabulary, and how short it is

Nets (EE2) ¶

The question you can answer: are these two pins connected?

The drawing is not the circuit. A schematic is a rendering of a netlist, several things that look like connections are not, and several connections are invisible. Checked by the integrity category and the structural half of connectivity.

• The same part, different jobs, reading a part from what it connects to
• The drawing is a rendering, what actually gets built
• One dot changes the circuit, a junction dot, and the netlist without it
• Names are wires too, why renaming a net rewires a board
• Wires that reach nothing
• What the reader can and cannot see, why these checks live in the reader

Roles (EE3) ¶

The question you can answer: why is that resistor there?

Every part has a job, and there are about twenty recurring ones. This is the unlock: most of connectivity and power stops looking like arbitrary rules once you can name what a part is for.

• The decision procedure, a lookup table for any two-terminal part
• The recurring jobs, the twenty, with the rules attached to each
• The role, why a chip needs charge locally
• A crystal is not an oscillator, where the oscillator actually is
• What the capacitors decide, load capacitance and frequency
• Presence is checkable, value is not
• Nothing is a voltage nothing has, why a floating input is not zero
• Some pins can only pull one way, open-drain
• One net, one decider, and what two deciders costs
• Two nets, opposite problems
• Pins the designer said to leave alone
• Most parts do not care, which parts have an orientation at all
• Here is one, wired backwards
• What the tool has to know, the two facts a polarity check needs

Failure modes (EE4) ¶

The question you can answer: how does this break, and what does the bench see?

A defect has a symptom, not just a state. Some faults never appear at power-on, which is what makes them expensive. This is the level at which severity, the Impact field and triage become readable.

• The failure mode, why missing decoupling is a warning
• Why this one is an error, and why the other is not
• The same fault on a rail, plus why a passing rule proves nothing
• The same wiring, on a different part, is correct, why a topology is not a verdict

Numbers (EE5) ¶

The question you can answer: is this within spec, and which datasheet row says so?

Absolute maximum against recommended operating, derating, tolerance, worst case. A claim you cannot trace to a row in a document is an opinion. Checked by the datasheet category over the parameter layer.

• The numbers, voltage rating, derating, and DC bias
• Choosing the resistor, which way a pull-up can be wrong, in both directions
• More is worse, why adding load capacitors can be the defect
• A part is a contract, the type-signature model
• Two numbers that look alike, absolute maximum against recommended operating
• A third number, which promises nothing, the typical column and why it is not a limit
• The comparison
• Where did the number come from?, provenance and the trust floor
• What this layer does not cover, why coverage is bounded by the corpus

Systems (EE6) ¶

The question you can answer: what has to come up first, and what feeds what?

A board is a power tree with a sequence, a current budget, and interfaces carrying requirements. This is where the design-intent layer and the profile/ family live.

• A board is fed by a cascade, reading a power tree off its regulators

• Nothing here is a fact about the world, why this level needs a declaration

• Enough current to go round, capacity against margin

• Order matters, and the datasheet says so, why a chip cares which rail arrives first

• Declared, then checked, the enable chain in copper

• The same board, declared differently

• What a part reads on the way up, straps and address collisions

• A bus is a contract, what a standard requires beyond two wires

• Declared once, checked everywhere, profiles and interface hosts

• The trap in that file, supersession switching checks off silently

• What a satisfied requirement says, and why the set a rule examined has to be declared rather than inferred

Layout (EE7) ¶

The question you can answer: why must that capacitor be at the pin?

Where a part physically sits changes what it does electrically. The board category and the geometry tier.

• The copper, why a netlist check cannot finish the job
• The promises this chapter is here to keep
• What geometry can answer, clearance, track width, annular ring
• A fourth kind of authority, where a fabrication limit comes from
• The netlist did not change

Chapter 12 is the one properly about this level.