12. When the copper matters

The last chapter. Everything so far treated a design as a graph; the board is a physical object, and a whole class of defect lives only there.

Every chapter so far has treated a design as a graph. Parts, nets, what connects to what. That model got us a long way, and it has been quietly deferring one thing since chapter 3.

A board is a physical object with copper on it, and the copper has width, position, and neighbours.

Read the whole course so far first. This chapter is mostly about why the earlier ones stopped where they did.

This page teaches at EE7, and the levels page says what each level means.

The promises this chapter is here to keep (EE7)

Three earlier chapters pointed at this one.

Chapter 3 took a decoupling capacitor on the correct net, placed 20 mm from the pin. That capacitor does not decouple the pin, because the loop it forms with the chip has enough inductance to defeat it at the frequencies it was fitted for. Same netlist, working or not working depending on where it sits.

Chapter 11 said the stray capacitance of the tracks counts toward a crystal’s load, so the same oscillator schematic runs at two frequencies on two layouts.

And chapter 1 put termination on its list of jobs. Termination only means anything because a track is a transmission line. Whether a track acts as one depends on its physical length relative to the signal on it.

None of those is checkable from a netlist. All of them are ordinary.

What geometry can answer (EE7)

Give the tool the copper and a different class of question opens up:

$ agni check --verdicts --rule copper-clearance --rule annular-width --rule track-width cmd/agni/testdata/conformance/drc.fires.kicad_pcb
annular-width  1 fail, 4 pass
    fail  THINRING   net has 1 via(s) with an annular ring below the 0.075mm floor
    pass  CLOSE_A    passes because thin is 0, not >= 1
    pass  CLOSE_B    passes because thin is 0, not >= 1
    pass  SMALLHOLE  passes because thin is 0, not >= 1
    pass  THIN       passes because thin is 0, not >= 1

copper-clearance  1 fail
    fail  CLOSE_A + CLOSE_B  copper of "CLOSE_A" and "CLOSE_B" closer than the 0.127mm
                             fabrication floor at 1 place(s); worst gap 0.040mm near (10.00,
                             -12.00)mm

track-width  1 fail, 4 pass
    fail  THIN       net has 1 track segment(s) narrower than the 0.127mm fabrication floor
    pass  CLOSE_A    passes because thin is 0, not >= 1
    pass  CLOSE_B    passes because thin is 0, not >= 1
    pass  SMALLHOLE  passes because thin is 0, not >= 1
    pass  THINRING   passes because thin is 0, not >= 1

11 verdicts across 3 rule(s), 8 pass, 3 fail

Three rules, and each verdict carries something no earlier chapter’s did.

copper-clearance names a pair and a place. CLOSE_A + CLOSE_B, with worst gap 0.040mm near (10.00, -12.00)mm. Two nets that should be electrically separate have copper running closer than the process can reliably keep apart, and the verdict carries a coordinate because “these two are too close” is unactionable without knowing where. Chapter 9 used the same pair-shaped subject for sequencing, for the same reason. The defect is a relation rather than a property.

track-width and annular-width name a net and a count. One track segment below 0.127mm, one via whose ring of copper is below 0.075mm. Neither is a connectivity question at all. The net is connected; it is connected by metal too thin to be made reliably.

Cross-section of a four-layer board. A drilled hole plated with copper joins a track on the top layer to a track on the bottom layer, and the two inner layers pull their copper back so the barrel passes without touching them. top layer inner layer inner layer bottom layer drill diameter plated barrel annular ring one net, on two layers, joined by the plated hole

A fourth kind of authority (EE7)

Look at where those numbers come from. The source is none of the ones the course has met so far.

0.127mm is not a physical law and it is not in a component’s datasheet. It is the width a fabricator can hold. A different process, or more money, gets you a smaller number. A cheaper one may not manage this one.

So the course has now seen four different answers to “who says what is correct”:

  • Physics answers in chapters 1 through 6. A floating input drifts and a reversed LED does not conduct whatever anyone thinks.
  • A vendor answers in chapter 7, through the part’s own datasheet and the trust question that came with it.
  • Your own declaration answers in chapters 8 through 10, because nothing states what a rail was supposed to be until you do.
  • A manufacturing process answers here, with what can actually be built. That limit is a business relationship as much as an engineering fact.

A check is only as meaningful as the authority behind its threshold. When one fires, ask which of the four you are looking at, and the answer tells you what to do. You argue with a fab about clearance. You do not argue with a floating input.

The netclass-track-width and netclass-via-drill rules sit at the same tier and answer to a net class, which is your own declaration about how a particular group of nets should be routed. A power net wants more copper than a signal net because it carries more current, and nothing in the geometry says which is which.

The netlist did not change (EE7) 

$ agni check --verdicts --rule single-pin-net --rule duplicate-net-name --rule output-output-conflict cmd/agni/testdata/conformance/drc.fires.kicad_pcb
single-pin-net  5 fail
    fail  CLOSE_A    net has 1 connection(s) and nothing marks it no-connect
    fail  CLOSE_B    net has 1 connection(s) and nothing marks it no-connect
duplicate-net-name  5 pass
    pass  CLOSE_A    passes because claims is 1, not >= 2
    pass  CLOSE_B    passes because claims is 1, not >= 2
output-output-conflict  5 pass
    pass  CLOSE_A    passes because drivers is 0, not >= 2
    pass  CLOSE_B    passes because drivers is 0, not >= 2

CLOSE_A and CLOSE_B are two separate nets, correctly two, and the rules that could object to their connectivity do not. duplicate-net-name passes because each name is claimed once. output-output-conflict passes because neither has two things driving it. Both would go on passing if the gap were 0.004 mm instead of 0.04.

single-pin-net does fail, because a bare .kicad_pcb is a board fixture with one pad per net, so every net on it is a stub. That has nothing to do with the clearance and would fire identically on a board whose copper was a mile apart.

No netlist you could inspect would find the real defect here. Neither would a query you could write, or any amount of care with the schematic. The connectivity is right. The board is wrong.

A geometry pass says so with the same discipline:

$ agni check --verdicts --rule copper-clearance cmd/agni/testdata/conformance/drc.passes.kicad_pcb
copper-clearance  1 pass
    pass  GND + SIG  copper of "GND" and "SIG" comes close enough to measure in 1 place(s) on a
                     shared layer and never within the 0.127mm fabrication floor

1 verdicts across 1 rule(s), 1 pass

It states that the two nets never came within the floor and says in how many places it looked. That is the considered set from chapter 5 arriving at the board tier.

Everything before this chapter stops here. So the tool has a board tier rather than treating the schematic as the design. A netlist is a model, models leave things out, and this one leaves out exactly the things that get decided after the schematic is signed off.

What you can now answer

  • Why a decoupling capacitor’s position changes whether it works, and why chapter 3 could not check it. (EE7)
  • Why a clearance finding carries a coordinate when almost nothing else in the catalog does. (EE7)
  • Where a fabrication limit comes from, and how that differs from a datasheet limit. (EE7)
  • Why two nets can pass every connectivity rule in the catalog and still be a defective board. (EE7)

The rules this page explains

Rule Severity What it catches
copper-clearance error copper of two nets closer than the process floor
track-width warning a track segment below the fabrication minimum
annular-width warning a via whose ring of copper is too thin to drill reliably
netclass-track-width warning a net routed narrower than its declared class requires
netclass-via-drill warning a via drilled smaller than its declared class requires

The end of the course

Twelve chapters climb the ladder. Here is the shape they make, stated once.

You started able to name components. You can now look at an unfamiliar board, say what most of its parts are for, predict how each would fail and what the bench would see, check a part against its datasheet and cite the row, read its power tree and say what has to come up first, and know which questions only the copper answers.

More usefully, you can tell what a report did not look at. That has been the through-line since chapter 5’s pass on a broken net, through the not-considered verdicts, to chapter 10’s satisfied requirement, which used to produce no output at all. A tool that tells you what it checked is worth more than one that tells you it found nothing, and knowing the difference is most of what separates using a checker from trusting one.

Where to go next depends on what you want. The tutorials take one board from a first read to a checklist gating CI, which is the tool-shaped version of this course. The rules catalog now reads as a list of things you understand rather than a glossary. And building a check rule is the other side of it, where the reasoning in these chapters gets written down as something a machine runs.

Chapter 13 comes after the climb. It treats the built board as something a test engineer has to measure, and it reads best once the rest of the course is familiar.