3. Why every chip needs capacitors

Decoupling and bulk, explained at four levels, with the rules that check each one.

Open any board and you will find capacitors scattered around every chip, usually more of them than anything else. This page is about why, and it is the best single example of the level ladder, because the same capacitor is a different question at four different levels and the tool checks it at a different tier each time.

Read EE1 (you know a capacitor stores charge) and EE2 (you can read a schematic as a graph of nets) first.

This page teaches at EE3, EE4, EE5 and EE7, and the levels page says what each level means.

The role (EE3)

Why is that capacitor there?

A chip’s supply pin needs a local charge reservoir.

Everything else on this page follows from that sentence, and the word that matters is local. The obvious mental model is that the voltage regulator supplies the chip, so as long as the wire gets there, the chip is powered. That model is fine for a torch and wrong for a digital chip, and the reason is time.

When a chip’s output drivers switch, they all flip within a nanosecond or two of each other, and at that instant the chip demands a gulp of current it did not need a moment earlier. The current has to come down the trace from the regulator. But a trace has inductance, roughly 1nH per millimetre, and inductance is the property that resists a change in current:

V = L · di/dt

Put numbers on it. A 50mm trace is about 50nH. Suppose the chip’s demand rises by 100mA over 10ns, so di/dt is 10⁷ amps per second. Then V = 50×10⁻⁹ × 10⁷ = 0.5V. Half a volt is dropped across a piece of copper, at exactly the moment the chip is busiest. On a 3.3V part that is a 15% sag on the supply, appearing and vanishing in nanoseconds.

A capacitor sitting at the supply pin already holds charge and has almost no inductance between it and the pin. It supplies that gulp locally and recharges slowly from the regulator afterwards. The regulator handles the average and the capacitor handles the transient.

A regulator feeding a chip through a long inductive trace, with a 100nF capacitor from the rail to ground right at the chip's supply pin supplies the average about 50 nH of trace inductance regulator chip outputs switching supply pin 100 nF at the pin supplies the fast gulp ground

Two jobs, two rules:

  • A decoupling capacitor sits at each supply pin and handles the fast transients. → decoupling-present
  • A bulk capacitor is larger, one per rail rather than one per pin, and handles slower swings such as a whole subsystem waking up. → bulk-cap

Run the first of those on the tutorial board and read what it concluded about each rail:

$ agni check --verdicts --rule decoupling-present examples/tutorial-project/designs/gateway/gateway.edn
decoupling-present  1 fail, 2 pass
    fail  PMIC_MAIN_12V0  no capacitor sits on the rail, which feeds at least one power-input
                          pin
    pass  PMIC_CORE_3V3   capacitor C1 sits on the rail
    pass  PMIC_IO_1V8     capacitor C3 sits on the rail

3 verdicts across 1 rule(s), 2 pass, 1 fail

The passes are the interesting part. They name the capacitor, so you can open the schematic and confirm that C1 really is on PMIC_CORE_3V3. That is the difference between a check that ran and a check that found nothing.

bulk-cap is deliberately absent from that run. It scopes on rails the design NAMES. It finds them through a net attribute, and only the schematic-geometry readers set that attribute. So on this EDIF board it has no subject at all and reports nothing. Printing that beside the decoupling verdicts would read as “the bulk capacitors are fine”, when the rule never looked at one. It is filed as agni issue 426.

The failure mode (EE4)

How does this break, and what does the bench see?

Here is the finding on its own:

$ agni check --rule decoupling-present examples/tutorial-project/designs/gateway/gateway.edn
findings by rule:
  decoupling-present     1

first 1:
  [warning] decoupling-present: PMIC_MAIN_12V0 (power rail has no decoupling capacitor)

1 finding(s) total
3 subject(s) considered by 1 rule(s) (--verdicts for the detail)

The severity is warning, not error. The EE4 content of this rule is in that choice. The naive reading says a missing decoupling cap is obviously serious and should be an error.

It is serious. It is a warning anyway because the board works, and a board that works makes the fault expensive.

A board with no decoupling on a rail powers up, runs, and passes bring-up. It fails later and intermittently: when many outputs happen to switch at once, when the enclosure is warm, on three units out of ten and not the other seven. On the bench you see a spontaneous reset, a corrupted register read, an ADC that is noisier than it should be, a link that drops once an hour. None of those symptoms points at a capacitor. Engineers lose weeks to this class of fault, and they lose them at the end of a project rather than the beginning.

The rule’s own Impact field says it in one line: “Rarely visible at first power-on, expensive to find later.”

This is the general shape of EE4. So severity in this catalog is a policy signal rather than a confidence signal. An error is something that will not work at all, like an I2C bus with no pull-up, which cannot signal even once. A warning is something that usually indicates a defect but where the board still runs. Missing decoupling is the archetype of the second, with the largest eventual cost and the smallest immediate symptom.

The numbers (EE5)

Is this within spec, and which datasheet row says so?

At EE3 the answer was “a capacitor”. At EE5 you have to say which capacitor, and now two numbers matter.

The first is capacitance, and the chip vendor states what the part needs, typically 100nF at each supply pin plus a shared bulk capacitor of a few µF to tens of µF. That number is in the datasheet, and you cannot deduce it from the schematic. So it lives in the parameter layer rather than in a netlist rule.

The second is the voltage rating. A capacitor has a maximum working voltage. On a rail above that rating it fails by a known mechanism, so the rating is more than a guideline. Ceramic capacitors fail short, and an overstressed decoupling cap becomes a dead short from the rail to ground. cap-voltage checks it, with a derating factor, because running a part at exactly its rating leaves nothing for tolerance or transients:

$ agni check --rule cap-voltage --params cmd/agni/testdata/conformance/params cmd/agni/testdata/conformance/capcheck.fires.kicad_sch
findings by rule:
  cap-voltage            1

first 1:
  [error] cap-voltage: C1 (capacitor C1 (MPN DEMO-CAP-6V3): rated voltage VDC 6.3V is below 12.5V required (rail "/+10V" 10V x derate 1.25) — datasheet "DEMO-CAP-6V3 Datasheet Rev A" page 2, "Ratings" (hand, confidence 1))

1 finding(s) total

Read the finding closely, because its structure is the EE5 skill in miniature. It states the observed value (6.3V rated), the required value (12.5V), how the requirement was computed (rail 10V × derate 1.25), and the datasheet page and table it came from. If you cannot trace an EE5 claim to a row in a document, the claim is an opinion.

A third number catches people, and nothing in this catalog checks it yet. A ceramic capacitor’s capacitance falls as you apply DC voltage to it. Class II dielectrics (X5R, X7R) can lose more than half their marked value at their rated voltage. A 100nF 6.3V X7R on a 5V rail may deliver under 50nF in circuit, so a design that looked correct on the schematic is short of decoupling on the bench. Class I dielectrics (C0G/NP0) do not do this, and cost more for the same capacitance. The usual working habit is to specify a voltage rating well above the rail, often 2× or more, for capacitance stability rather than for breakdown margin.

The copper (EE7)

Why must that capacitor be at the pin?

Everything above is netlist-level, meaning the capacitor is on the right net, with the right value and rating. A board can satisfy all of it and still have no working decoupling.

The reason is the same inductance from EE3, now applied to the capacitor’s own path. A decoupling cap does its job through a loop: out of the cap, into the supply pin, through the chip, out of the ground pin, back to the cap. That loop has inductance proportional to its physical area. Place the cap 20mm away, or route its ground back through a long trace instead of straight down into a ground plane, and the loop inductance swamps the capacitor at exactly the frequencies it was there for.

The same capacitor, the same net and the same value, placed twice. On the left it sits at the chip's supply pin and the current loop it closes encloses a small area. On the right it sits across the board and the same loop encloses a much larger one. Loop inductance follows that area, so only geometry tells the two apart; a netlist reads them as identical. at the pin across the board chip chip 100 nF 100 nF a small loop the same loop, three times the area the cap still supplies the gulp the inductance swamps the cap both boards have the same netlist, the same part and the same value on the same two nets reading a netlist can prove a capacitor is present, and only geometry can say whether it is close

The rule says so itself, in its remedy: “Add a decoupling capacitor from the rail to ground at each supply pin, and place it at the pin in layout. A capacitor drawn on the rail but placed across the board does not decouple it.”

This is a genuine limit of a netlist check rather than a gap someone forgot to fill. The rule’s scope note says explicitly that placement is a board-tier notion. Limits like this one are the reason the tool has a board tier at all. Reading a netlist can prove a capacitor is present; only geometry can say whether it is close.

What you can now answer

  • Why a chip needs a capacitor a few millimetres away when a regulator is already supplying it. (EE3)
  • Why missing decoupling is a warning rather than an error, and what it looks like on the bench. (EE4)
  • What a voltage rating means, why a derate factor exists, and why “100nF” on a schematic may not be 100nF in the circuit. (EE5)
  • Why the netlist check stops where it does, and what a board-tier check would have to add. (EE7)

The rules this page explains

Rule Level What it checks
decoupling-present EE3 a rail feeding supply pins carries at least one capacitor
bulk-cap EE3 a named rail carries any capacitor at all
cap-voltage EE5 a capacitor’s rated voltage clears its rail, with derating, cited to a datasheet

The next chapter, Pull-ups and undefined states, runs the same shape of argument over a resistor.